The present invention relates to an integrated circuit, and more particularly, to an integrated circuit configured to control on/off timing of an on-die-termination (ODT) operation for impedance control in a semiconductor device to prevent malfunctions of the semiconductor device.
Semiconductor devices are implemented into integrated circuit (IC) chips such as central processing units (CPUs), memories, and gate arrays, and are incorporated into a variety of electrical products such as personal computers, servers and workstations. Most semiconductor devices include a receiving circuit configured to receive external signals from an outside world through input pads and an output circuit configured to provide internal signals to an outside world through output pads.
As the operating speed of electrical products is increasing, a swing width of a signal exchanged between semiconductor devices is being gradually reduced for minimizing a delay time taken for signal transmission. However, the reduction in the swing width of the signal increases an influence of an external noise on the signal and causes the signal reflectance to become more critical at an interface terminal due to impedance mismatch. Such impedance mismatch is generally caused by an external noise, a variation of a power supply voltage, a change in an operating temperature, a change in a manufacturing process, etc. The impedance mismatch may lead to a difficulty in high-speed transmission of data and distortion in output data. Therefore, if semiconductor devices receive the distorted output signal through an input terminal, it frequently gives rise to problems such as a setup/hold failure and an error in decision of an input level.
In order to resolve the above problems, a memory device to requiring high-speed performance employs an impedance matching circuit, which is called an ODT circuit, near an input pad inside an IC chip.
FIG. 1 is a block diagram of a typical ODT circuit and a typical ODT control circuit provided to a DDR2 semiconductor memory device.
The ODT control circuit includes an ODT buffer 110, a setup/hold delay 120, a clock generator 130, a shift register 140, and a controller 150 to control the ODT circuit 160.
The ODT buffer 110 buffers an on/off control signal ODT received from an external controller to enable/disable ODT operations.
The setup/hold delay 120 delays the buffered on/off control signal ODTI by a predetermined delay time to secure a setup/hold margin.
The clock generator 130 receives output clocks RCLKDLL and FCLKDLL of the delay locked loop (DLL) to generate shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3 having different phases, in a non-power-down mode (i.e., when a clock enable signal CKE has a logic low level).
The shift register 140 delays the delayed on/off control signal ODT_SH received from the setup/hold delay 120 in synchronization with the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3. Logic levels of the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3 are fixed to a logic high level in a power-down mode, whereas they are toggled in the non-power-down mode. Accordingly, the shift register 140 delays the delayed on/off control signal ODT_SH only in a non-power mode.
The shift register 140 also receives resistance information signals ODT0, ODT1 and ODT2 from an extended mode register set (EMRS) to determine termination resistance of the ODT circuit 160 according to which signals among the resistance information signals ODT0, ODT1 and ODT2 are activated. For example, the termination resistance of the ODT circuit 160 is 150Ω when the resistance information signal ODT0 is activated, 75Ω when the resistance information signals ODT0 and ODT1 are activated, and 50Ω when all the resistance information signals ODT0, ODT1 and ODT2 are activated. The shift register 140 delays the delayed on/off control signal ODT_SH in synchronization with the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3, and outputs signals selected among combined on/off control signals ODTOUT0, ODTOUT1 and ODTOUT2 according to the activated signals among the resistance information signals ODT0, ODT1 and ODT2. Here, output timing of the combined on/off control signals ODTOUT0, ODTOUT1 and ODTOUT2 depends on the timing of the delayed on/off control signal ODT_SH. Which signal among the combined on/off control signals ODTOUT0, ODTOUT1 and ODTOUT2 is activated depends on which signal among the resistance information signals ODT0, ODT1 and ODT2 is input.
The controller 150 decodes the combined on/off control signals ODTOUT0, ODTOUT1 and ODTOUT2 received from the shift register 140 to activate at least one of ODT control signals SW0_UP, SW1_UP, SW2_UP, SW0_DN, SW1_DN and SW2_DN, thereby turning on/off resistors in the ODT circuit 160.
The enable circuit 170 shown at the left side of FIG. 1 receives the resistance information signals ODT0, ODT1 and ODT2. If at least one signal among the resistance information signals ODT0, ODT1 and ODT2 is activated, the enable circuit 170 activates an enable signal ODTENB to enable the ODT buffer 110, the clock generator 130 and the shift register 140.
In summary, timing for turning on/off the ODT circuit 160 is determined by a delay time of the on/off control signal ODT. The delay time is determined by transferring the on/off control signal ODT from an external controller or chipset to the shift resistor 140 via the ODT buffer 110 and the setup/hold delay 120. In addition, the resistance of the ODT circuit 160 is determined by the resistance information signals ODT0, ODT1 and ODT2 activated by the EMRS. More detailed description of the operation of the ODT control circuit will be described later with reference to FIG. 5.
FIG. 2 is a circuit diagram of the ODT circuit 160 of FIG. 1.
Referring to FIG. 2, the ODT circuit 160 includes a plurality of resistors 161 to 166 for terminating an input/output node DQ in a pull-up direction or in a pull-down direction. The resistors 161 to 166 are turned on/off in response to ODT control signals SW0_UP, SW0_DN, SW1_UP, SW1_DN, SW2_UP and SW2_DN received from the controller 150.
For example, when the termination resistance is set to 150, the resistors 161 and 162 are turned on in response to the ODT control signals SW0_UP and SW0_DN to terminate the input/output node DQ with a resistance of 150. Similarly, when the termination resistance is set to 75, the resistors 161, 162, 163 and 164 are turned on, and when the termination resistance is set to 50, all the resistors 161, 162, 163, 164, 165 and 166 are turned on.
FIG. 3 is a circuit diagram of a shift register 140 shown in FIG. 1.
Referring to FIG. 3, the shift register 140 includes pass gates PG1, PG2, PG3, PG4 and PG5 which are turned on/off in response to an internal clock CK0 and shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2, FCLKDLL3. Here, the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2, FCLKDLL3 with different phases are generated by the output clocks FCLKDLL and RCLKDLL of the DLL.
In a non-power-down mode (i.e., when the clock enable signal CKE has a logic high level), if at least one of the resistance information signals ODT0, ODT1 and ODT2 are activated, the enable signal ODTENB is activated to a logic low level. Then, the shift register 140 becomes able to receive the delayed on/off control signal ODT_SH. While the internal clock CK0 is at a logic high level, the delayed on/off control signal ODT_SH is transferred to a node ND. Thereafter, the delayed on/off control signal ODT_SH is transferred further sequentially in response to the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2, FCLKDLL3. Then, a NAND operation is performed on a first internal delayed on/off control signal ODTOND before the pass gate PG5 and a second internal delayed on/off control signal ODTOFFD after the pass gate PG5 to activate a shifted on/off control signal ODTS.
Then, NAND operations are performed on the shifted on/off control signal ODTS and the resistance information signals ODT0, ODT1 and ODT2 received from the EMRS to activate combined on/off control signals ODTOUT0, ODTOUT1 and ODTOUT2, respectively. Accordingly, the combined on/off control signals ODTOUT0, ODTOUT1 and ODTOUT2 have information about resistances according to the resistance information signals ODT0, ODT1 and ODT2, respectively, as well as information about on/off timing of an ODT operation according to the delayed on/off control signal ODTS.
In a power-down mode (i.e., when the clock enable signal CKE has a logic low level), logic levels of the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3 are all fixed to a logic high level to reduce lo current consumption. Accordingly, the pass gates PG2, PG3, PG4 and PG5 are all turned on, and thus the delayed on/off control signal ODT_SH passes through the shift register 140 without being shifted in response to the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3.
FIG. 4 is a circuit diagram of a clock generator 130 shown in FIG. 1.
In a non-power-down mode, the clock generator 130 receives a rising clock RCLKDLL and a falling clock FCLKDLL from the DLL to reduce pulse widths thereof and then shift phases thereof, thereby outputting the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3. In a power-down mode, the clock generator 130 fixes logic levels of the rising and falling clocks RCLKDLL and FCLKDLL to a logic high level. Therefore, the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3 are not generated.
Upper portion of FIG. 4 illustrates a portion of the clock generator 130 for receiving the rising clock RCLKDLL to generate the shift clocks RCLKDLL0 and RCLKDLL2, and a lower portion of FIG. 4 illustrates a portion of the clock generator 130 for receiving the falling clock FCLKDLL to generate shift clocks FCLKDLL1 and FCLKDLL3. Except that input signals and output signals thereof are different from each other, operations of the two portions are identical to each other. Therefore, only the portion of the clock generator 130 for receiving the rising clock RCLKDLL to generate the shift clocks RCLKDLL0 and RCLKDLL2 will be described below.
When the termination resistance is determined (i.e., at least one of the resistance information signals ODT0, ODT1 and ODT2 in FIG. 1 is activated), the inverter 401 is enabled. Passing through the inverters 401, 402 and 403, the rising clock RCLKDLL is delayed by a predetermined delay time. While the rising clock RCLKDLL passes through the inverter 401, a delay time of a falling edge thereof is longer than that of a rising edge thereof because the inverter 401 has resistance only in a pull-up direction. On the contrary, while the rising clock RCLKDLL passes through the inverter 402, a delay time of the rising edge thereof is longer than that of the falling edge thereof because the inverter 402 has resistance only in a pull-down direction. A NAND gate 404 performs a NAND operation on the rising clock RCLKDLL output from the inverter 403 and the original rising clock RCLKDLL to reduce pulse width of the rising clock RCLKDLL.
In a non-power-down mode, because the clock enable signal CKE has a logic high level, the NAND gate 408 reduces pulse width of the rising clock RCLKDLL. The delay lines 409 and 410 shift phase of the rising clock RCLKDLL output from the NAND gate 408 to output shift clocks RCLKDLL0 and RCLKDLL2.
FIG. 5 is a timing diagram illustrating operations of the typical ODT control circuit (shown in FIGS. 1 and 3) in the non-power-down mode and the power-down mode.
To begin with, the non-power-down mode where the clock enable signal CKE has a logic high level will be described. For convenience of explanation, the case where only the resistance information signal ODT0 among the resistance information signals ODT0, ODT1 and ODT2 is activated, i.e., the case where the termination resistance is set to 150Ω by EMRS will be described.
If the resistance information signal ODT0 is activated, the enable signal ODTENB is activated to a logic low level by the enable circuit 170. Then, the ODT buffer 110 and the shift register 140 are enabled. The on/off control signal ODT_SH is input from the external controller and then pass through the ODT buffer 110 and the setup/hold delay 120 to be output to the shift register 140 as a delayed on/off control signal ODT_SH. In the shift register 140, the delayed on/off control signal ODT_SH passes through the pass gate PG1 in response to the internal clock CLK0, and then sequentially transferred to the node NC and to the node ND. Thereafter, the delayed on/off control signal ODT_SH sequentially transferred further to the node NF, to the node NH and then to the node NI, in response to the RCLKDLL0, FCLKDLL1 and RCLKDLL2, respectively. The first internal delayed on/off control signal ODTOND before the pass gate PG5 which is turned on/off in response to the shift signal FCLKDLL3 and the second internal delayed on/off control signal ODTOFFD after the pass gate PG5 pass through respective delays. A NAND operation is performed on the first internal delayed on/off control signal ODTOND and the second internal delayed on/off control ODTOFD to activate a shifted on/off control signal ODTS.
Then, a NAND operation is performed on the shifted on/off control signal ODTS and the resistance information signal ODT0 activated by the EMRS to activate the combined on/off control signal ODTOUT0. Accordingly, the combined on/off control signal ODTOUT0 has information about resistance according to the resistance information signals ODT0, ODT1 and ODT2 as well as information about on/off timing of the ODT operation according to the shifted on/off control signal ODTS.
In the power-down mode where the clock enable signal CKE has a logic low level, the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3 are all fixed to a logic high level to reduce current consumption. Accordingly, the delayed on/off control signal ODT_SH passes through the shift register 140 without being delayed in synchronization with the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3. Therefore, the combined on/off control signal ODTOUT0 is activated and deactivated without being delayed sufficiently.
As described above, since delay of the delayed on/off control signal in response to the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3 does not take place in the power-down mode, on/off timing of the ODT operation in the power-down mode is advanced more than in the non-power-down mode. Therefore, during the operation of a memory device in one slot (for example, in a PC, a DRAM installed in one memory slot among a plurality of memory slots), ODT operation of a memory device in a power-down mode in another slot may be performed amiss, causing a failure.